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[Other resource] vhdl实现alu的源代码

Description: VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
Platform: | Size: 1740 | Author: 飞扬 | Hits:

[Documents] how to write testbench

Description: 很好的，适合初学者Writing Efficient Testbenches
Platform: | Size: 196792 | Author: applehot@126.com | Hits:

[SourceCode] VHDL_Testbench

Description: VHDL中TestBench的编写，很详细，有例程
Platform: | Size: 7363164 | Author: evistera | Hits:

[VHDL-FPGA-Verilog] 比较器的测试矢量

Description: 一个很好的testbench的例子。
Platform: | Size: 3934 | Author: daxuerushui | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] flash接口控制_verilog

Description: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Platform: | Size: 870400 | Author: 李楠 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Platform: | Size: 111616 | Author: 孙犁 | Hits:

[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4096 | Author: 张雷 | Hits:

[VHDL-FPGA-Verilog] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[Other] lab4

Description: VHDL traffic light control
Platform: | Size: 80896 | Author: yeqing | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] RISCMCU

Description: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Platform: | Size: 594944 | Author: wutailiang | Hits:

[Software Engineering] TestBench_writing

Description: testbench书写规范格式的ppt教程
Platform: | Size: 20480 | Author: ZHUOHUI LI | Hits:

[Other] testbench

Description: 32位除法器的测试程序， 由随机向量产生函数产生一组随机数 来验证计算书否正确-32 divider test procedures, by the random vector generated a set of functions to generate random numbers to verify whether the correct calculation of the book
Platform: | Size: 5120 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] Test_Bench

Description: 8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言，开发环境：FPGA)-Eight test vectors (Test_Bench) and example of waveform generator (VHDL language, development environment: FPGA)
Platform: | Size: 12288 | Author: 11 | Hits:

[VHDL-FPGA-Verilog] dac

Description: DAC converter design with Verilog code and testbench
Platform: | Size: 527360 | Author: 田磊 | Hits:

[VHDL-FPGA-Verilog] color_converter.tar

Description: 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助-This code different image color conversion between formats, such as XYZ <-> RGB, different standards of RGB <-> RGB and RGB <-> YCbCr conversion between packet contains code m file matlab simulation, VHDL code . v documents and ModelSim Simulation Testbench documentation, I believe everyone will certainly help
Platform: | Size: 339968 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] spi_boot-rel_3_2_rev_C.tar

Description: spi bootloader详细资料，里面包含C代码和VHDL代码以及testbench以及相关的说明文档，有兴趣的朋友可以下来看看。-spi bootloader detailed information, which contains C code and VHDL code and Testbench and related documentation, interested friends can see them.
Platform: | Size: 192512 | Author: zheng jun | Hits:

[Other] ArtofWritingTestBenches

Description: Art of Writing TestBenches：极经典的testbench书写入门书籍，能够让初学者在短时间内掌握testbench的书写步骤，对testbench有一个初步的认识，这是一个verilog方面的，没找到verilog就选了开发环境为vhdl-Art of Writing TestBenches: very classic entry Testbench writing books, that allows beginners to master in a short time Testbench writing steps Testbench have a preliminary understanding, this is a Verilog area, could not find Verilog development environment on selected for VHDL
Platform: | Size: 97280 | Author: 侯浩 | Hits:

[VHDL-FPGA-Verilog] trueif

Description: 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
Platform: | Size: 1024 | Author: QU YIFAN | Hits:
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